PipeFL: Hardware/Software co-Design of an FPGA Accelerator for Federated Learning

Federated learning has solved the problems of data silos and fragmentation on premise satisfying privacy. However, cryptographic algorithms in federated brought significant increase computational complexity, which limited speed model training. In this paper, we propose a hardware/software (HW/SW) co-designed field programmable gate array (FPGA) accelerator for learning. Firstly, analyzed time consumption each stage involved algorithms, found performance bottleneck. Secondly, HW/SW architecture is introduced, can up encryption, decryption ciphertext-space computation at same without reconfiguring FPGA circuit. HW part, proposed Hardware-aware Montgomery Algorithm (HWMA) utilized parallelism pipeline, designed an to decouple access computation. SW Operator Scheduling Engine (OSE) designed, flexibly resolve target algorithm into multiple HWMA calls, complete other non-computation-intensive calculations. Finally, evaluations both specific practical applications are implemented. Experimental results show that when deployed Intel Stratix 10 FPGA, our throughput 2048-bit modular multiplication, exponentiation Paillier more than 3x CPU. When integrated industrial grade open source framework, end-to-end training linear regression logistic be shortened by 2.28x 3.30x respectively, 2x faster reported best accelerator.